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? 2011 microchip technology inc. ds25073a-page 1 mcp6n11 features rail-to-rail input and output gain set by 2 external resistors minimum gain (g min ) options: 1, 2, 5, 10 or 100 v/v common mode rejection ratio (cmrr): 115 db (typical, g min =100) power supply rejection ratio (psrr): 112 db (typical, g min =100) bandwidth: 500 khz (typical, gain = g min ) supply current: 800 a/channel (typical) single channel enable/v os calibration pin: (en/cal ) power supply: 1.8v to 5.5v extended temperature range: -40c to +125c typical applications high side current sensor wheatstone bridge sensors difference amplifier with level shifting power control loops design aids microchip advanced part selector (maps) demonstration board application notes block diagram description microchip technology inc. offers the single mcp6n11 instrumentation amplifier (ina) with enable/v os cali- bration pin (en/cal ) and several minimum gain options. it is optimized for single-supply operation with rail-to-rail input (no common mode crossover distor- tion) and output performance. two external resistors set the gain, minimizing gain error and drift-over temperature. the reference voltage (v ref ) shifts the output voltage (v out ). the supply voltage range (1.8v to 5.5v) is low enough to support many portable applications. all devices are fully specified from -40c to +125c. these parts have five minimum gain options (1, 2, 5, 10 and 100 v/v). this allows the user to optimize the input offset voltage and input noise for different applications. typical application circuit package types r f v fg v out low power v ss v dd en/cal v out v os calibration v ref r m4 g m2 i 2 v ref i 4 g m3 i 3 v tr r g v ip v im g m1 i 1 v ip v im por 10 v dd i dd v bat +1.8v to +5.5v v out v ref v fg r f r g 200 k 10 k u 1 mcp6n11 mcp6n11 soic v ip v im v ss v dd v out 1 2 3 4 8 7 6 5 v ref en/cal v fg mcp6n11 23 tdfn * v ip v im v ss v dd v out 1 2 3 4 8 7 6 5 v ref en/cal v fg * includes exposed thermal pad (ep); see table 3-1 . ep 9 500 khz, 800 a instru mentation amplifier downloaded from: http:///
mcp6n11 ds25073a-page 2 ? 2011 microchip technology inc. minimum gain options table 1 shows key specifications that differentiate between the different minimum gain (g min ) options. see section 1.0 electrical characteristics , section 6.0 packaging information and product identification system for further information on g min . table 1: key differentiating specifications part no. g min (v/v) nom. v os (mv) max. ? v os / ? t a (v/c) typ. cmrr (db) min. v dd =5.5v psrr (db) min. v dmh (v) max. gbwp (mhz) nom. e ni (v p-p ) nom. (f = 0.1 to 10 hz) e ni (nv/ hz) nom. (f = 10 khz) mcp6n11-001 1 3.0 90 70 62 2.70 0.50 570 950 mcp6n11-002 2 2.0 45 78 68 1.35 1.0 285 475 mcp6n11-005 5 0.85 18 80 75 0.54 2.5 114 190 mcp6n11-010 10 0.50 9.0 81 81 0.27 5.0 57 95 mcp6n11-100 100 0.35 2.7 88 86 0.027 35 18 35 downloaded from: http:///
? 2011 microchip technology inc. ds25073a-page 3 mcp6n11 1.0 electrical characteristics 1.1 absolute maximum ratings ? v dd Cv ss .......................................................................6.5v current at input pins ?? ...............................................2 ma analog inputs (v ip and v im ) ?? ..... v ss C 1.0v to v dd +1.0v all other inputs and outputs ......... v ss C 0.3v to v dd +0.3v difference input voltage....................................... |v dd Cv ss | output short circuit current ................................ continuous current at output and supply pins ............................30 ma storage temperature ...................................-65c to +150c max. junction temperature ........................................ +150c esd protection on all pins (hbm, cdm, mm) . 2 kv, 1.5 kv, 300v ?notice: stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. ?? see section 4.2.1.2 input voltage limits and section 4.2.1.3 input current limits . 1.2 specifications table 1-1: dc electrical specifications electrical characteristics: unless otherwise indicated, t a =+25c, v dd = 1.8v to 5.5v, v ss = gnd, en/cal =v dd , v cm =v dd /2, v dm =0v, v ref =v dd /2, v l =v dd /2, r l =10k to v l and g dm =g min ; see figure 1-6 and figure 1-7 . parameters sym min typ max units g min conditions input offset input offset voltage, calibrated v os -3.0 +3.0 mv 1 ( note 2 ) -2.0 +2.0 mv 2 -0.85 +0.85 mv 5 -0.50 +0.50 mv 10 -0.35 +0.35 mv 100 input offset voltage trim step v ostrm 0 . 3 6m v1 0 . 2 1m v2 0 . 0 7 7m v5 0 . 0 4 5m v1 0 0 . 0 1 4m v1 0 0 input offset voltage drift v os / t a 9 0 / g min v/c 1 to 10 t a = -40c to +125c ( note 3 ) 2.7 v/c 100 power supply rejection ratio psrr 62 82 db 1 68 88 db 2 75 96 db 5 81 102 db 10 86 112 db 100 note 1: v cm = (v ip + v im ) / 2, v dm = (v ip C v im ) and g dm = 1 + r f /r g . 2: the v os spec limits include 1/f noise effects. 3: this is the input offset drift without v os re-calibration; toggle en/cal to minimize this effect. 4: these specs apply to both the v ip , v im input pair (use v cm ) and to the v ref , v fg input pair (v ref takes v cm s place). 5: this spec applies to the v ip , v im , v ref and v fg pins individually. 6: figure 2-11 and figure 2-19 show the v ivr and v dmr variation over temperature. 7: see section 1.5 explanation of dc error specs . downloaded from: http:///
mcp6n11 ds25073a-page 4 ? 2011 microchip technology inc. input current and impedance ( note 4 ) input bias current i b 10 pa all across temperature 80 pa t a = +85c across temperature 0 2 5 na t a = +125c input offset current i os 1p a across temperature 5 pa t a = +85c across temperature -1 0.05 +1 na t a = +125c common mode input impedance z cm 1 0 13 ||6 ||pf differential input impedance z diff 1 0 13 ||3 ||pf input common mode voltage (v cm or v ref ) ( note 4 ) input voltage range v ivl v ss ? 0.2 v all ( note 5 , note 6 ) v ivh v dd +0.15 v common mode rejection ratio cmrr 62 79 db 1 v cm = v ivl to v ivh , v dd =1.8v 69 87 db 2 75 101 db 5 79 107 db 10 86 119 db 100 70 94 db 1 v cm = v ivl to v ivh , v dd =5.5v 78 100 db 2 80 108 db 5 81 114 db 10 88 115 db 100 common mode non-linearity inl cm -1000 115 +1000 ppm 1 v cm = v ivl to v ivh , v dm =0v, v dd =1.8v ( note 7 ) -570 27 +570 ppm 2 -230 11 +230 ppm 5 -125 6 +125 ppm 10 -50 2 +50 ppm 100 -400 42 +400 ppm 1 v cm = v ivl to v ivh , v dm =0v, v dd =5.5v ( note 7 ) -220 10 +220 ppm 2 -100 4 +100 ppm 5 -50 2 +50 ppm 10 -30 1 +30 ppm 100 table 1-1: dc electrical specifications (continued) electrical characteristics: unless otherwise indicated, t a =+25c, v dd = 1.8v to 5.5v, v ss = gnd, en/cal =v dd , v cm =v dd /2, v dm =0v, v ref =v dd /2, v l =v dd /2, r l =10k to v l and g dm =g min ; see figure 1-6 and figure 1-7 . parameters sym min typ max units g min conditions note 1: v cm = (v ip + v im ) / 2, v dm = (v ip C v im ) and g dm = 1 + r f /r g . 2: the v os spec limits include 1/f noise effects. 3: this is the input offset drift without v os re-calibration; toggle en/cal to minimize this effect. 4: these specs apply to both the v ip , v im input pair (use v cm ) and to the v ref , v fg input pair (v ref takes v cm s place). 5: this spec applies to the v ip , v im , v ref and v fg pins individually. 6: figure 2-11 and figure 2-19 show the v ivr and v dmr variation over temperature. 7: see section 1.5 explanation of dc error specs . downloaded from: http:///
? 2011 microchip technology inc. ds25073a-page 5 mcp6n11 input differential mode voltage (v dm ) ( note 4 ) differential input voltage range v dml -2.7/g min va l l v ref = (v dd Cg dm v dm )/2 ( note 6 ) v dmh +2.7/g min v differential gain error g e - 1 0 . 1 3+ 1% v dm = v dml to v dmh , differential gain drift g e / t a 0.0006 %/c v ref = (v dd Cg dm v dm )/2 differential non-linearity inl dm -500 30 +500 ppm 1 ( note 7 ) -800 40 +800 ppm 2, 5 -2000 100 +2000 ppm 10, 100 dc open-loop gain a ol 61 84 db 1 v dd =1.8v, 68 90 db 2 v out = 0.2v to 1.6v 76 98 db 5 78 104 db 10 86 116 db 100 70 94 db 1 v dd =5.5v, 77 100 db 2 v out = 0.2v to 5.3v 84 108 db 5 90 114 db 10 97 125 db 100 output minimum output voltage swing v ol v ss +15 mv all v dm =-v dd /(2g dm ), v dd =1.8v, v ref = v dd /2 C 1v v ss +25 mv v dm =-v dd /(2g dm ), v dd =5.5v, v ref = v dd /2 C 1v maximum output voltage swing v oh v dd ? 15 mv v dm =v dd /(2g dm ), v dd =1.8v, v ref = v dd /2 + 1v v dd ? 25 mv v dm =v dd /(2g dm ), v dd =5.5v, v ref = v dd /2 + 1v output short circuit current i sc 8m a v dd = 1.8v 3 0m a v dd = 5.5v power supply supply voltage v dd 1.8 5.5 v all quiescent current per amplifier i q 0.5 0.8 1.1 ma i o = 0 por trip voltage v prl 1.1 1.4 v v prh 1 . 41 . 7v table 1-1: dc electrical specifications (continued) electrical characteristics: unless otherwise indicated, t a =+25c, v dd = 1.8v to 5.5v, v ss = gnd, en/cal =v dd , v cm =v dd /2, v dm =0v, v ref =v dd /2, v l =v dd /2, r l =10k to v l and g dm =g min ; see figure 1-6 and figure 1-7 . parameters sym min typ max units g min conditions note 1: v cm = (v ip + v im ) / 2, v dm = (v ip C v im ) and g dm = 1 + r f /r g . 2: the v os spec limits include 1/f noise effects. 3: this is the input offset drift without v os re-calibration; toggle en/cal to minimize this effect. 4: these specs apply to both the v ip , v im input pair (use v cm ) and to the v ref , v fg input pair (v ref takes v cm s place). 5: this spec applies to the v ip , v im , v ref and v fg pins individually. 6: figure 2-11 and figure 2-19 show the v ivr and v dmr variation over temperature. 7: see section 1.5 explanation of dc error specs . downloaded from: http:///
mcp6n11 ds25073a-page 6 ? 2011 microchip technology inc. table 1-2: ac electrical specifications electrical characteristics: unless otherwise indicated, t a =25c, v dd = 1.8v to 5.5v, v ss = gnd, en/cal =v dd , v cm =v dd /2, v dm =0v, v ref =v dd /2, v l =v dd /2, r l =10k to v l , c l = 60 pf and g dm =g min ; see figure 1-6 and figure 1-7 . parameters sym min typ max units g min conditions ac response gain bandwidth product gbwp 0.50 g min mhz 1 to 10 35 mhz 100 phase margin pm 70 all open-loop output impedance r ol 0 . 9k 1 to 10 0 . 6k 100 power supply rejection ratio psrr 94 db all f < 10 khz common mode rejection ratio cmrr 104 db 1 to 10 f < 10 khz 94 db 100 f < 10 khz step response slew rate sr 3 v/s 1 to 10 v dd =1.8v 9 v / s v dd =5.5v 2 v/s 100 v dd =1.8v 6 v / s v dd =5.5v overdrive recovery, input common mode t irc 1 0 s a l lv cm =v ss C1v (or v dd + 1v) to v dd /2, g dm v dm = 0.1v, 90% of v out change overdrive recovery, input differential mode t ird 5 s v dm =v dml C(0.5v)/g min (or v dmh +(0.5v)/g min ) to 0v, v ref =(v dd Cg dm v dm )/2, 90% of v out change overdrive recovery, output t or 8 s g dm =2g min , g dm v dm =0.5v dd to 0v, v ref =0.75v dd (or 0.25v dd ), 90% of v out change noise input noise voltage e ni 570/g min v p-p 1 to 10 f = 0.1 hz to 10 hz 1 8 v p-p 100 input noise voltage density e ni 950/g min nv/ hz 1 to 10 f = 100 khz 3 5 n v / hz 100 input current noise density i ni 1 f a / hz all f = 1 khz downloaded from: http:///
? 2011 microchip technology inc. ds25073a-page 7 mcp6n11 table 1-3: digital electrical specifications electrical characteristics: unless otherwise indicated, t a = 25c, v dd = 1.8v to 5.5v, v ss = gnd, en/cal =v dd , v cm = v dd /2, v dm =0v, v ref =v dd /2, v l =v dd /2, r l =10k to v l , c l = 60 pf and g dm =g min ; see figure 1-6 and figure 1-7 . parameters sym min typ max units g min conditions en/cal low specifications en/cal logic threshold, low v il v ss 0.2v dd va l l en/cal input current, low i enl -0.1 na en/cal = 0v gnd current i ss -7 -2.5 a en/cal = 0v, v dd =5.5v amplifier output leakage i o(leak) 10 na en/cal = 0v en/cal high specifications en/cal logic threshold, high v ih 0.8 v dd v dd va l l en/cal input current, high i enh -0.01 na en/cal = v dd en/cal dynamic specifications en/cal input hysteresis v hyst 0.2 va l l en/cal low to amplifier output high-z turn-off time t off 3 10 s en/cal = 0.2v dd to v out = 0.1(v dd /2), v dm g dm = 1 v, v l =0v en/cal high to amplifier output on time t on 12 20 28 ms en/cal = 0.8v dd to v out = 0.9(v dd /2), v dm g dm = 1 v, v l =0v en/cal low to en/cal high low time t enlh 100 s minimum time before externally releasing en/cal ( note 1 ) amplifier on to en/cal low setup time t enol 1 0 0 s por dynamic specifications v dd to output off t phl 1 0 sa l lv l =0v, v dd = 1.8v to v prl C0.1v step, 90% of v out change v dd to output on t plh 140 250 360 ms v l =0v, v dd = 0v to v prh +0.1v step, 90% of v out change note 1: for design guidance only; not tested. table 1-4: temperature specifications electrical characteristics: unless otherwise indicated, all limits are specified for: v dd = 1.8v to 5.5v, v ss = gnd. parameters sym min typ max units conditions temperature ranges specified temperature range t a -40 +125 c operating temperature range t a -40 +125 c ( note 1 ) storage temperature range t a -65 +150 c thermal package resistances thermal resistance, 8l-soic ja 1 5 0 c / w thermal resistance, 8l-tdfn (23) ja 5 3 c / w note 1: operation must not cause t j to exceed the absolute maximum junc tion temperature specification (+150c). downloaded from: http:///
mcp6n11 ds25073a-page 8 ? 2011 microchip technology inc. 1.3 timing diagrams figure 1-1: common mode input overdrive recovery timing diagram. figure 1-2: differential mode input overdrive recovery timing diagram. figure 1-3: output overdrive recovery timing diagram. figure 1-4: por timing diagram. figure 1-5: en/cal timing diagram. v out t irc v dm v cm (1v)/g dm v out t ird v cm v dm v dd /2 v out t or v cm v dm v dd /2 1.8v v prl C0.1v high-z v out v dd t phl t plh v prh +0.1v 0v high-z v out en/cal t off t on t enlh t enol downloaded from: http:///
? 2011 microchip technology inc. ds25073a-page 9 mcp6n11 1.4 dc test circuits 1.4.1 input offset test circuit figure 1-6 is used for testing the inas input offset errors and input voltage range (v e , v ivl and v ivh ; see section 1.5.1 input offset related errors and section 1.5.2 input offset common mode non- linearity ). u 2 is part of a control loop that forces v out to equal v cnt ; u 1 can be set to any bias point. figure 1-6: test circuit for common mode (input offset). when mcp6n11 is in its normal range of operation, the dc output voltages are (where v e is the sum of input offset errors and g e is the gain error): equation 1-1: table 1-5 gives the recommended r f and r g values for different g min options. 1.4.2 differential gain test circuit figure 1-7 is used for testing the inas differential gain error, non-linearity and input voltage range (g e , inl dm , v dml and v dmh ; see section 1.5.3 differential gain error and non-linearity ). r f and r g are 0.01% for accurate gain error measurements. figure 1-7: test circuit for differential mode. the output voltages are (where v e is the sum of input offset errors and g e is the gain error): equation 1-2: to keep v ref , v fg and v out within their ranges, set: equation 1-3: table 1-6 shows the recommended r f and r g . they produce a 10 k load; v l can usually be left open. table 1-5: selecting r f and r g g min (v/v) nom. r f ( ) nom. r g ( ) nom. g dm (v/v) nom. g dm v os (v) max. bw (khz) nom. 1 100k 499 201.4 0.60 2.5 2 0.40 5.0 5 100k 100 1001 0.85 2.5 10 0.50 5.0 100 0.35 35 r l v cm 100 nf v dd 2.2 f v ref v l 12.7 k v m 100 nf c cnt u 1 mcp6n11 u 2 mcp6h01 v cnt 63.4 k r g r f r cnt 63.4 k v out 10 nf 1k 1k g dm 1r f r g ? + = v out v cnt = v m v ref g dm 1g e + () v e + = table 1-6: selecting r f and r g g min (v/v) nom. r f ( ) nom. r g ( ) nom. g dm (v/v) nom. 10o p e n 1 . 0 0 0 2 4.99k 4.99k 2.000 5 8.06k 2.00k 5.030 10 9.09k 1.00k 10.09 100 10.0k 100 101.0 r l 6.34 k 1k 1k v cm +v dm /2 + 100 nf v out r f r g v m C 100 nf v dd 2.2 f 6.34 k v ref v fg v l v cm Cv dm /2 0.01% 0.01% u 1 mcp6n11 g dm 1r f r g ? + = v m v out v ref ? = v out v ref g dm 1g e + () v dm v e + () + = g dm 1g e + () v dm v e + () = v ref v dd g dm v dm ? () 2 ? = downloaded from: http:///
mcp6n11 ds25073a-page 10 ? 2011 microchip technology inc. 1.5 explanation of dc error specs 1.5.1 input offset related errors the input offset error (v e ) is extracted from input offset measurements (see section 1.4.1 input offset test circuit ), based on equation 1-1 : equation 1-4: v e has several terms, which assume a linear response to changes in v dd , v ss , v cm , v out and t a (all of which are in their specified ranges): equation 1-5: equation 1-2 shows how v e affects v out . 1.5.2 input offset common mode non-linearity the input offset error (v e ) changes non-linearly with v cm . figure 1-8 shows v e vs. v cm , as well as a linear fit line (v e_lin ) based on v os and cmrr. the op amp is in standard conditions ( v out =0, v dm =0, etc.). v cm is swept from v ivl to v ivh . the test circuit is in section 1.4.1 input offset test circuit and v e is calculated using equation 1-4 . figure 1-8: input offset error vs. common mode input voltage. based on the measured v e data, we obtain the following linear fit: equation 1-6: the remaining error ( v e ) is described by the common mode non-linearity spec: equation 1-7: the same common mode behavior applies to v e when v ref is swept, instead of v cm , since both input stages are designed the same: equation 1-8: 1.5.3 differential gain error and non-linearity the differential errors are extracted from differential gain measurements (see section 1.4.2 differential gain test circuit ), based on equation 1-2 . these errors are the differential gain error (g e ) and the input offset error (v e , which changes non-linearly with v dm ): equation 1-9: these errors are adjusted for the expected output, then referred back to the input, giving the differential input error (v ed ) as a function of v dm : equation 1-10: v e v m v ref ? g dm 1g e + () --------------------------------- = where: psrr , cmrr and a ol are in units of v/v t a is in units of c v dm =0 v e v os v dd v ss ? psrr --------------------------------- v cm cmrr ---------------- - v ref cmrr ---------------- - ++ + = v out a ol ----------------- t a v os t a ------------- ? ++ v 1 v 3 v e , v e_lin (v) v cm (v) v ivl v ivh v dd /2 v 2 v e_lin v e v e where: v e_lin v os v cm v dd 2 ? ? cmrr ---------------------------------- - + = v os v 2 = 1 cmrr ---------------- - v 3 v 1 ? v ivh v ivl ? ----------------------------- - = where: inl cm max v e v ivh v ivl ? ----------------------------- - = v e v e v e_lin ? = v e_lin v os v ref v dd 2 ? ? cmrr ------------------------------------ - + = inl cm max v e v ivh v ivl ? ----------------------------- - = g dm 1r f r g ? + = v m g dm 1g e + () v dm v+ e () = v ed v m g dm ----------- -v dm ? = downloaded from: http:///
? 2011 microchip technology inc. ds25073a-page 11 mcp6n11 figure 1-9 shows v ed vs. v dm , as well as a linear fit line (v ed_lin ) based on v e and g e . the op amp is in standard conditions ( v out =0, etc.). v dm is swept from v dml to v dmh . figure 1-9: differential input error vs. differential input voltage. based on the measured v ed data, we obtain the following linear fit: equation 1-11: note that the v e value measured here is not as accurate as the one obtained in section 1.5.1 input offset related errors . the remaining error ( v ed ) is described by the differential mode non-linearity spec: equation 1-12: v 1 v 3 v ed , v ed_lin (v) v dm (v) v dml v dmh 0 v 2 v ed_lin v ed v ed where: v ed_lin 1g e + () v e g e v dm + = g e v 3 v 1 ? v dmh v dml ? ----------------------------------- 1 ? = v e v 2 1g e + --------------- - = where: inl dm max v ed v dmh v dml ? ----------------------------------- = v ed v ed v ed_lin ? = downloaded from: http:///
mcp6n11 ds25073a-page 12 ? 2011 microchip technology inc. notes: downloaded from: http:///
? 2011 microchip technology inc. ds25073a-page 13 mcp6n11 2.0 typical performance curves note: unless otherwise indicated, t a = +25c, v dd = 1.8v to 5.5v, v ss = gnd, en/cal =v dd , v cm = v dd /2, v dm =0v, v ref =v dd /2, v l =v dd /2, r l = 10 k to v l , c l = 60 pf and g dm = g min ; see figure 1-6 and figure 1-7 . 2.1 dc voltages and currents figure 2-1: normalized input offset voltage, with g min = 1 to 10. figure 2-2: normalized input offset voltage, with g min = 100. figure 2-3: normalized input offset voltage drift, with g min = 1 to 10. figure 2-4: normalized input offset voltage drift, with g min = 100. note: the graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. the performance characteristics listed herein are not tested or guaranteed. in some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. 30% 35% es 330 samples t a = 25% 30% rrence t a +25c v dd = 1.8v and 5.5v rto 20% f occu g min = 1 g min =2to10 10% 15% tage of g min =2to10 5% 10% percent 0% 0 6 2 8 4 0 4 8 2 6 0 p -2. 0 -1. 6 -1. 2 -0. 8 -0. 4 0. 0 0. 4 0. 8 1. 2 1. 6 2. 0 normalized input offset voltage; g min v os (mv) 12% 14% s 330 samples g min = 100 10% 12% rrence min t a = +25c v dd = 1.8v and 5.5v rto 8% f occu 6% t age o f 2% 4% p ercen t 0% 2% p -18-16 -14 -12 -10 -8-6 -4 -2 02 4 6 8 1012 14 16 18 normalized input offset voltage; g min v os (mv) 25% c es no v os re-calibration 330 sam p les 20% c urren c p g min = 1 to 10 v dd = 5.5v rto 15% of oc c 10% e ntage 5% perc e 0% 600500 4 00 300 2 00 100 0 100 2 00 300 4 00 500600 -- - 4 -- 2 - 2 4 normalized input offset voltage drift; g min (v os /t a ) (v/c) 16% 18% c es no v os re-calibration 330 sam p les 12% 14% c urren c p g min = 100 v dd = 5.5v rto 8% 10% of oc c 4% 6% 8% e ntage 0% 2% 4% perc e 0% 1 200 1 000 -800-600 -400 -200 0 200400 600 800 1 000 1 200 - 1 - 1 1 1 normalized input offset voltage drift; g min (v os /t a ) (v/c) downloaded from: http:///
mcp6n11 ds25073a-page 14 ? 2011 microchip technology inc. note: unless otherwise indicated, t a = +25c, v dd = 1.8v to 5.5v, v ss = gnd, en/cal =v dd , v cm = v dd /2, v dm =0v, v ref =v dd /2, v l =v dd /2, r l = 10 k to v l , c l = 60 pf and g dm = g min ; see figure 1-6 and figure 1-7 . figure 2-5: normalized input offset voltage vs. power supply voltage, with v cm = 0v and g min =1 to 10. figure 2-6: normalized input offset voltage vs. power supply voltage, with v cm = 0v and g min =100. figure 2-7: normalized input offset voltage vs. power supply voltage, with v cm =v dd and g min = 1 to 10. figure 2-8: normalized input offset voltage vs. power supply voltage, with v cm =v dd and g min = 100. figure 2-9: normalized input offset voltage vs. output voltage, with g min = 1 to 10. figure 2-10: normalized input offset voltage vs. output voltage, with g min = 100. -0.5 0.0 0.5 1.0 1.5 2.0 2.5 d input offset voltage; g min v os (mv) -40c -2.5 -2.0 -1.5 -1.0 0.00.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 normalized g power supply voltage representative part v cm = v ss g min = 1 to 10 rto +25c+85c +12 5 c 20 25 a ge; 10 15 e t volt a 0 5 10 t offs e s (mv) -5 0 d inpu t g min v o -15 -10 m alize d g representative partv cm = v ss -40c 25c 85 c -25 -20 nor m cm ss g min = 100 rto 85 c 125c 0.00.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 power supply voltage - 04 -0.2 0.0 0.2 0.4 0.6 0.8 1.0 1.2 d input offset voltage; g min v os (mv) representative part v cm = v dd g min = 1 to 10 rto -40c+25c +85c +125 c -1.2 -1.0 -0.8 -0.6 - 0 . 4 0.00.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 normalize d g power supply voltage -2 0 2 4 6 8 10 d input offset voltage; g min v os (mv) representative part v cm = v dd g min = 100 rto -10 -8 -6 -4 0.00.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 normalized g power supply voltage -40c+25c +85c +125c -0.5 0.0 0.5 1.0 1.5 2.0 d input offset voltage; g min v os (mv) representative part g min = 1 to 10 rto v dd = 5.5v v dd = 1.8v -2.0 -1.5 -1.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 normalize d g output voltage (v) 2 -1 0 1 2 3 4 5 6 d input offset voltage; g min v os (mv) representative part g min = 100 rto v dd = 5.5v v dd = 1.8v -6 -5 -4 -3 - 2 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 normalize d g output voltage (v) downloaded from: http:///
? 2011 microchip technology inc. ds25073a-page 15 mcp6n11 note: unless otherwise indicated, t a = +25c, v dd = 1.8v to 5.5v, v ss = gnd, en/cal =v dd , v cm = v dd /2, v dm =0v, v ref =v dd /2, v l =v dd /2, r l = 10 k to v l , c l = 60 pf and g dm = g min ; see figure 1-6 and figure 1-7 . figure 2-11: input common mode voltage headroom vs. ambient temperature. figure 2-12: normalized input offset voltage vs. common mode voltage, with v dd = 1.8v and g min =1 to 10. figure 2-13: normalized input offset voltage vs. common mode voltage, with v dd = 1.8v and g min =100. figure 2-14: normalized input offset voltage vs. common mode voltage, with v dd = 5.5v and g min = 1 to 10. figure 2-15: normalized input offset voltage vs. common mode voltage, with v dd = 5.5v and g min =100. figure 2-16: normalized cmrr and psrr vs. ambient temperature. 0.4 0.5 o m 1 wafer lot v ivh Cv dd 0.2 0.3 h eadro o 00 0.1 0.2 a nge h v ) v dd = 1.8v 02 -0.1 0 . 0 t age r a ( v dd v dd = 5.5v -0.3 - 0 . 2 ut vol t -0.5 -0.4 inp v ivl Cv ss -50 -25 0 25 50 75 100 125 ambient temperature (c) -0.5 0.0 0.5 1.0 1.5 2.0 d input offset voltage; g min v os (mv) v dd = 1.8v representative part g min = 1 to 10 rto -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 normalized g input common mode voltage (v) +125c +85c+25c -40c -5 0 5 10 15 d input offset voltage; g min v os (mv) v dd = 1.8v representative part g min = 100 rto -15 -10 -5 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 normalized g input common mode voltage (v) +125c +85c+25c -40c -0.5 0.0 0.5 1.0 1.5 2.0 d input offset voltage; g min v os (mv) v dd = 5.5v representative part g min = 1 to 10 rto +125c +85 -2.0 -1.5 -1.0 -0.5 0.00.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 normalized g input common mode voltage (v) +85c+25c -40c -5 0 5 10 15 d input offset voltage; g min v os (mv) v dd = 5.5v representative part g min = 100 rto -15 -10 -5 -0.5 0.00.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 normalized g input common mode voltage (v) +125c +85c+25c -40c 105 110 b ) cmrr / g min , v dd = 1.8v: g min = 1 100 cmrr / g min , v dd = 5.5v: g min = 1to10 95 100 p srr; g min (d b g min 1 , 100 g min = 2 to 10 g min 1to10 g min = 100 85 90 95 m rr, p s rr / g 80 85 ized c m g min , p s 70 75 n ormal rr / g psrr / g min : 60 65 n cm psrr / g min : g min = 1 to 10 g min = 100 60 -50 -25 0 25 50 75 100 125 ambient temperature (c) downloaded from: http:///
mcp6n11 ds25073a-page 16 ? 2011 microchip technology inc. note: unless otherwise indicated, t a = +25c, v dd = 1.8v to 5.5v, v ss = gnd, en/cal =v dd , v cm = v dd /2, v dm =0v, v ref =v dd /2, v l =v dd /2, r l = 10 k to v l , c l = 60 pf and g dm = g min ; see figure 1-6 and figure 1-7 . figure 2-17: normalized dc open-loop gain vs. ambient temperature. figure 2-18: the mcp6n11 shows no phase reversal vs. common mode voltage. figure 2-19: normalized differential mode voltage range vs. ambient temperature. figure 2-20: normalized differential input error vs. differential voltage, with g min =1. figure 2-21: normalized differential input error vs. differential voltage, with g min = 2 to 100. figure 2-22: the mcp6n11 shows no phase reversal vs. differential voltage, with v dd =5.5v. 105 110 a in; 95 100 o op g a ) v dd = 5.5v v dd = 1.8v 85 90 95 o pen-l o m in (db ) 80 85 d dc o a ol / g m 70 75 m alize d a g min = 1 to 10 g = 100 60 65 nor m g min = 100 -50 -25 0 25 50 75 100 125 ambient temperature (c) 5.5 6.0 representative part v dd = 5.5v 40 4.5 5.0 (v) dd g dm = 100 30 3.5 4 . 0 o ltage g dm 100 g dm = 1 2.0 2.5 3 . 0 t put v o v im = -0.20v 1.0 1.5 2.0 ou t v im = v dd + 0.15v 0.0 0.5 -1.0-0.5 0.00.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 non-inverting input voltage; v ip (v) 3.8 4.0 u t v ) 1 wafer lot g min v dmh = -g min v dml 3.4 3.6 i al inp u v dmh ( v rto 30 3.2 3.4 f ferent i e ; g min v 2.8 3 . 0 z ed di f rang e 2.4 2.6 o rmali z o ltage 2.0 2.2 n o v o note: for g min = 1, v dmh = minimum of plot value and v dd -50 -25 0 25 50 75 100 125 axis title - 2 -1 0 1 2 3 4 5 ized differential input r or; g min v ed (mv) representative part v ed = (v out Cv ref )/g dm Cv dm g min = 1 rto v dd = 1.8v v dd = 5.5v -5 -4 -3 2 -5-4-3-2-1012345 normal er r normalized differential input voltage; g min v dm (v) 4 5 p ut representative part v ed = (v out C v ref )/g dm C v dm 2 3 t ial in p mv) v ed (v out v ref )/g dm v dm g min = 2 to 100 rto 0 1 i fferen t m in v ed ( - 2 -1 0 ized d i r or; g m - 4 -3 2 n ormal er r -5 4 - 5 - 4 - 3 - 2 - 1 0 1 2 3 4 5 n - 5 - 4 - 3 - 2 - 1 0 1 2 3 4 5 normalized differential input voltage; g min v dm (v) 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 t put voltage (v) representative part v dd = 5.5v v ref = (v dd Cg dm v dm )/2 0.0 0.5 1.0 1.5 -7-6-5-4-3-2-101234567 ou t differential input voltage (v) g min = 1 g min = 2 g min = 5 g min = 10 g min = 100 downloaded from: http:///
? 2011 microchip technology inc. ds25073a-page 17 mcp6n11 note: unless otherwise indicated, t a = +25c, v dd = 1.8v to 5.5v, v ss = gnd, en/cal =v dd , v cm = v dd /2, v dm =0v, v ref =v dd /2, v l =v dd /2, r l = 10 k to v l , c l = 60 pf and g dm = g min ; see figure 1-6 and figure 1-7 . figure 2-23: input bias and offset currents vs. ambient temperature, with v dd = +5.5v. figure 2-24: input bias current vs. input voltage (below v ss ). figure 2-25: input bias and offset currents vs. common mode input voltage, with t a = +85c. figure 2-26: input bias and offset currents vs. common mode input voltage, with t a = +125c. figure 2-27: output voltage headroom vs. output current. figure 2-28: output voltage headroom vs. ambient temperature. 1.e-10 1.e-09 1.e-08 s , offset currents (a) v dd = 5.5v v cm = v dd i b 100p 1n 10n 1.e-12 1.e-11 25 45 65 85 105 125 input bia s ambient temperature (c) | i os | 1p 10p 1e09 1.e-08 1.e-07 1.e-06 1.e-05 1.e-04 1.e-03 urrent magnitude (a) +125c +85 c +25c -40 1m 100 10 1 100n 10n 1n 1.e-12 1.e-11 1.e-10 1.e-09 -1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0 input cu input voltage (v) -40 c 1n 100p 10p 1p -20 0 20 40 60 80 100 s, offset currents (pa) representative part t a = +85c v dd = 5.5v i b i os -100 -80 -60 -40 0.00.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 input bias common mode input voltage (v) 10 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 s, offset currents (na) representative part t a = +125c v dd = 5.5v i b i os -2.5 -2.0 -1.5 -1.0 0.00.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 input bias common mode input voltage (v) 1000 m v) o om ( m v =18v v dd = 5.5v 100 h eadr o v dd =1 . 8v 100 ltage h v dd Cv oh v v put vo v ol C v ss 10 out 10 0.1 1 10 output current magnitude (ma) 9 10 7 8 (mv) v dd Cv oh 5 6 7 d room v dd = 5.5v 4 5 u t hea d 2 3 outp u v dd = 1.8v 0 1 v ol Cv ss 0 -50 -25 0 25 50 75 100 125 ambient temperature (c) downloaded from: http:///
mcp6n11 ds25073a-page 18 ? 2011 microchip technology inc. note: unless otherwise indicated, t a = +25c, v dd = 1.8v to 5.5v, v ss = gnd, en/cal =v dd , v cm = v dd /2, v dm =0v, v ref =v dd /2, v l =v dd /2, r l = 10 k to v l , c l = 60 pf and g dm = g min ; see figure 1-6 and figure 1-7 . figure 2-29: output short circuit current vs. power supply voltage. figure 2-30: supply current vs. power supply voltage. figure 2-31: supply current vs. common mode input voltage. -10 0 10 20 30 40 50 ort circuit current (ma) +125c +85c +25c -40c -50 -40 -30 -20 0.00.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 output sho power supply voltage (v) 400 500 600 700 800 900 1000 1100 ply current (a) +125c +85c +25c 40 0 100 200 300 0.00.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 sup power supply voltage (v) -40c 1000 1100 800 900 a) v dd = 5.5v 600 700 u rrent ( v dd = 1.8v 400 500 ply c u 200 300 sup 0 100 -0.5 0.00.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 common mode input voltage (v) downloaded from: http:///
? 2011 microchip technology inc. ds25073a-page 19 mcp6n11 note: unless otherwise indicated, t a = +25c, v dd = 1.8v to 5.5v, v ss = gnd, en/cal =v dd , v cm = v dd /2, v dm =0v, v ref =v dd /2, v l =v dd /2, r l = 10 k to v l , c l = 60 pf and g dm = g min ; see figure 1-6 and figure 1-7 . 2.2 frequency response figure 2-32: cmrr vs. frequency. figure 2-33: psrr vs. frequency. figure 2-34: normalized open-loop gain vs. frequency. figure 2-35: normalized gain bandwidth product and phase margin vs. ambient temperature. figure 2-36: closed-loop output impedance vs. frequency. figure 2-37: gain peaking vs. normalized capacitive load. 40 50 60 70 80 90 100 cmrr (db) g min = 1 v dd = 5.5v 0 10 20 30 1.e+03 1.e+04 1.e+05 1.e+06 frequency (hz) g min 1 g min = 2 g min = 5 g min = 10 g min = 100 1k 10k 100k 1m 110 120 v dd = 5.5v 80 90 100 60 70 80 r (db) 40 50 60 psr r 20 30 40 g min = 1 g min = 2 g min = 5 0 10 20 min g min = 10 g min = 100 1.e+03 1.e+04 1.e+05 1.e+06 frequency (hz) 1k 10k 100k 1m -90 -60 100 120 n n - 150 -120 60 80 o p gai () o p gai n (db) a ol /g min 210 -180 - 150 20 40 60 p en-lo o o l /g min p en-lo o a ol /g mi n | a ol /g min | -240 - 210 0 20 z ed o p a se; a o z ed o p t ude; a -300 -270 -40 -20 o rmali z ph a o rmali z m agni t g min = 1 g min = 2 g =5 -360 -330 -80 -60 n o n o m g min =5 g min = 10 g min = 100 1.e+4 1.e+5 1.e+6 1.e+7 frequency (hz) 10k 100k 1m 10m 140 150 0.45 0.50 h ) 120 130 035 0.40 ) n dwit h n (mhz ) 100 110 120 025 0.30 0 . 35 a rgin ( a in ba n w p/g mi n g min = 1 g min = 2 gbwp 90 100 0.20 0 . 25 h ase m a i zed g a t ; gb w min g min = 5 g min = 10 g min = 100 gbwp pm 70 80 0.10 0.15 p h n ormal i roduc t 50 60 0.00 0.05 n p -50 -25 0 25 50 75 100 125 ambient temperature (c) 1.e+04 n ce 10k m peda n g dm /g min = 10 g min = 1 to 10 1.e+03 t put i m ) 1k g dm /g min 10 min 1e+02 o p ou t ( 100 g min = 100 1 . e+02 s ed-lo o 100 1e+01 clo s g dm /g min = 1 10 1 . e+01 1.e+03 1.e+04 1.e+05 1.e+06 1.e+07 frequency (hz) 10 1k 10k 100k 1m 10m 6 7 g min = g dm = 1 g min = 10 5 6 b) g min g dm 1 = 2 = 5 = 10 g dm = 20 = 50 4 5 k ing (d = 100 3 n pea k g min = 100 g dm = 200 = 500 2 gai 0 1 0 1.e+1 1.e+2 1.e+3 normalized capacitive load; c l (g min /g dm ) (f) 10p 100p 1n downloaded from: http:///
mcp6n11 ds25073a-page 20 ? 2011 microchip technology inc. note: unless otherwise indicated, t a = +25c, v dd = 1.8v to 5.5v, v ss = gnd, en/cal =v dd , v cm = v dd /2, v dm =0v, v ref =v dd /2, v l =v dd /2, r l = 10 k to v l , c l = 60 pf and g dm = g min ; see figure 1-6 and figure 1-7 . 2.3 noise figure 2-38: normalized input noise voltage density vs. frequency. figure 2-39: normalized input noise voltage density vs. input common mode voltage, with f = 100 hz. figure 2-40: normalized input noise voltage density vs. input common mode voltage, with f = 10 khz. figure 2-41: normalized input noise voltage vs. time, with g min = 1 to 10. figure 2-42: normalized input noise voltage vs. time, with g min = 100. 1000 a ge 1m rto 100 e volt a / hz) 100 10 u t nois e n e ni (v / 10 g min = 100 10 e d inp u t y; g mi 10 1 r maliz e densi t 1 g min = 10 g min = 5 g min = 2 0.1 no r 100n g min 2 g min = 1 1.e-1 1.e+0 1.e+1 1.e+2 1.e+3 1.e+4 1.e+5 1.e+6 frequency (hz) 0.1 100 1k 1 10 100k 1m 10k 12 14 e 10 12 voltag hz) g = 100 8 noise e ni (v/ v dd = 1.8v v dd = 5.5v g min = 100 g min = 10 g min = 5 g min =2 6 input ; g min e g min = 2 g min = 1 2 4 m alized e nsity ; 0 2 nor m d e f = 100 hzrto -0.5 0.00.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 common mode input voltage (v) 35 4.0 e 3.0 3 . 5 voltag hz) 20 2.5 noise e ni (v/ v dd = 1.8v v dd = 5.5v g min = 100 g min = 10 g min = 5 1.5 2 . 0 input ; g min e min g min = 2 g min = 1 05 1.0 m alized e nsity ; 0.0 0 . 5 nor m d e f = 10 khzrto -0.5 0.00.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 common mode input voltage (v) 0.4 0.5 representative partg min = 1 to 10 analog npbw = 0.1 hz sam p le rate = 4 sps 02 0.3 n oise; ) min rto p 00 0.1 0 . 2 nput n t ) (mv ) -0.1 0 . 0 a lized i g min e ni ( t -0.3 -0.2 norm a g -0.5 -0.4 0 5 10 15 20 25 30 35 time (min) 15 2.0 representative partg min = 100 analog npbw = 0.1 hz sam p le rate = 4 sps 1.0 1 . 5 n oise; ) min rto p 00 0.5 nput n t ) (mv ) -0.5 0 . 0 a lized i g min e ni ( t -1.0 norm a g -2.0 -1.5 0 5 10 15 20 25 30 35 time (min) downloaded from: http:///
? 2011 microchip technology inc. ds25073a-page 21 mcp6n11 note: unless otherwise indicated, t a = +25c, v dd = 1.8v to 5.5v, v ss = gnd, en/cal =v dd , v cm = v dd /2, v dm =0v, v ref =v dd /2, v l =v dd /2, r l = 10 k to v l , c l = 60 pf and g dm = g min ; see figure 1-6 and figure 1-7 . 2.4 time response figure 2-43: small signal step response. figure 2-44: large signal step response. figure 2-45: slew rate vs. ambient temperature. figure 2-46: maximum output voltage swing vs. frequency. figure 2-47: common mode input overdrive recovery time vs. normalized gain. figure 2-48: differential input overdrive recovery time vs. normalized gain. ) v dd = 5.5v g dm = g min m v/div ) r f + r g = 10 k e (10 m g min =1to10 voltag g min = 1 to 10 g min = 100 o utput o 0 2 4 6 8 10 12 14 16 18 20 time (s) 5.0 5.5 ) v dd = 5.5v g dm = g min 4.0 4.5 m v/div ) dm min r f + r g = 10 k 3.0 3.5 e (10 m 2.0 2.5 v oltag e g min = 1 to 10 g min = 100 1.0 1.5 o utput v 0.0 0.5 o 0.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 time (s) 9 10 7 8 s ) 5 6 7 t e (v/ s g 1t 10 v =55v 4 5 e w ra t g min = 1t o 10 g min = 100 v dd =5 . 5v v dd = 1.8v 2 3 sl e 0 1 -50 -25 0 25 50 75 100 125 ambient temperature (c) 10 ing ge sw v dd = 5.5v 1 t volta -p ) v dd = 1.8v 1 outpu (v p g min = 1 to 10 g min = 100 x imum 0 ma x 0 1.e+4 1.e+5 1.e+6 frequency (hz) 10k 100k 1m 1000 g e s ) g dm v dm = 1v 100 volta g t irc ( s v dd = 5.5v 100 n mode o very; v dd = 1.8v dd 10 o mmo n v e rec o 10 p ut c o v erdri v g min = 100 1 in p o v g min = 1 g min = 10 1 10 100 normalized gain; g dm /g min 1000 a ge s ) 100 e volt a t ird ( s v dd = 5.5v 100 a l mod e o very; v dd = 1.8v v dd 5.5v 10 e renti a v e rec o 10 p ut diff e v erdri v g min = 100 1 in p o v g min = 1 g min = 10 1 10 100 normalized gain; g dm /g min downloaded from: http:///
mcp6n11 ds25073a-page 22 ? 2011 microchip technology inc. note: unless otherwise indicated, t a = +25c, v dd = 1.8v to 5.5v, v ss = gnd, en/cal =v dd , v cm = v dd /2, v dm =0v, v ref =v dd /2, v l =v dd /2, r l = 10 k to v l , c l = 60 pf and g dm = g min ; see figure 1-6 and figure 1-7 . figure 2-49: output overdrive recovery time vs. normalized gain. figure 2-50: the mcp6n11 shows no phase reversal vs. common mode input overdrive, with v dd =5.5v. figure 2-51: the mcp6n11 shows no phase reversal vs. differential input overdrive, with v dd =5.5v. 10 100 1000 t overdrive recovery; t or (s) g min = 10 g dm = 2g min v ref = 0.75v dd g min = 1 v dd = 1.8v v dd = 5.5v 1 10 1 10 100 outpu normalized gain; g dm /g min g min = 100 5 6 u t v dd = 5.5v g dm v dm =+ 0.1v v cm 4 5 , outp u g dm v dm 0.1v f = 10 khz 3 mode , e s (v) 2 mmon v oltag e v g 1 0 1 p ut co v v out , g min = 1 v out , g min = 100 -1 0 in p 0 102030405060708090100 time (s) 3 4 v dd = 5.5v v ip 2 3 g es (v) 0 1 volta g v out , g min = 1 v out , g min = 100 -1 0 o utput -2 n put, o -4 -3 i n v im 0 102030405060708090100 time (s) downloaded from: http:///
? 2011 microchip technology inc. ds25073a-page 23 mcp6n11 note: unless otherwise indicated, t a = +25c, v dd = 1.8v to 5.5v, v ss = gnd, en/cal =v dd , v cm = v dd /2, v dm =0v, v ref =v dd /2, v l =v dd /2, r l = 10 k to v l , c l = 60 pf and g dm = g min ; see figure 1-6 and figure 1-7 . 2.5 enable/calibration and por responses figure 2-52: en/cal and output voltage vs. time, with v dd =1.8v. figure 2-53: en/cal and output voltage vs. time, with v dd =5.5v figure 2-54: en/cal hysteresis vs. ambient temperature. figure 2-55: en/cal turn on time vs. ambient temperature. figure 2-56: power supply on and off and output voltage vs. time. figure 2-57: por trip voltages and hysteresis vs. temperature. 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 , output voltage (v) v dd = 1.8v v l = 0v ina turns off calibration starts ina turns on -0.2 0.0 0.2 0.4 0 102030405060708090100 en/cal time (ms) en/cal v out 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 , output voltage (v) v dd = 5.5v v l = 0v ina turns off calibration starts ina turns on -0.5 0.0 0.5 1.0 1.5 0 102030405060708090100 en/cal time (ms) en/cal v out 0.55 0.60 0.45 0.50 s (v) v dd = 5.5v 030 0.35 0.40 s teresi 020 0.25 0 . 30 a l hy s 0.10 0.15 0 . 20 en/c a v dd = 1.8v 0.00 0.05 0.10 -50 -25 0 25 50 75 100 125 ambient temperature (c) 30 m s) 25 ; t on ( m v dd = 5.5v 15 20 n time ; v dd = 1.8v 10 15 urn o n 5 10 / cal t 0 5 en / -50 -25 0 25 50 75 100 125 ambient temperature (c) 1.6 1.8 e (v) v l = 0v 12 1.4 v oltag e 08 1.0 1 . 2 u tput v on 0.6 0 . 8 ply, o u v dd v out on 0.2 0.4 e r sup off off -0.2 0.0 pow e calibrating off off 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 time (s) 006 0.08 0.10 0.12 0.14 0.16 0.18 11 1.2 1.3 1.4 1.5 1.6 1.7 r hysteresis (v) trip voltages (v) v prh Cv prl v prh 0.00 0.02 0.04 0 . 06 0.8 0.9 1.0 1 . 1 -50 -25 0 25 50 75 100 125 po r por ambient temperature (c) v prl downloaded from: http:///
mcp6n11 ds25073a-page 24 ? 2011 microchip technology inc. note: unless otherwise indicated, t a = +25c, v dd = 1.8v to 5.5v, v ss = gnd, en/cal =v dd , v cm = v dd /2, v dm =0v, v ref =v dd /2, v l =v dd /2, r l = 10 k to v l , c l = 60 pf and g dm = g min ; see figure 1-6 and figure 1-7 . figure 2-58: quiescent current in shutdown vs. power supply voltage. figure 2-59: output leakage current vs. output voltage. 0.0 e nt; en/cal = 0v -0.5 y curr e -1.0 s uppl y a) -1.5 p ower s i ss ( -2.0 ative p +125c +85 c -2.5 neg +85 c +25c -40c 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 power supply voltage (v) 1.e-07 a ) en/cal = 0v v dd = 5.5v 100n 1.e-08 r ent ( a +125c dd 10n 1.e-09 g e cur r +85c 1n 1.e-10 l eaka g 100p 1.e-11 u tput l 25 c 10p 1.e-12 o u + 25 c 1p 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 output voltage (v) 1p downloaded from: http:///
? 2011 microchip technology inc. ds25073a-page 25 mcp6n11 3.0 pin descriptions descriptions of the pins are listed in table 3-1 . 3.1 analog signal inputs the non-inverting and inverting inputs (v ip , and v im ) are high-impedance cmos inputs with low bias currents. 3.2 analog feedback input the analog feedback input (v fg ) is the inverting input of the second input stage. the external feedback components (r f and r g ) are connected to this pin. it is a high-impedance cmos input with low bias current. 3.3 analog reference input the analog reference input (v ref ) is the non-inverting input of the second input stage; it shifts v out to its desired range. the external gain resistor (r g ) is connected to this pin. it is a high-impedance cmos input with low bias current. 3.4 analog output the analog output (v out ) is a low-impedance voltage output. it represents the differential input voltage (v dm =v ip Cv im ), with gain g dm and is shifted by v ref . the external feedback resistor (r f ) is connected to this pin. 3.5 power supply pins the positive power supply (v dd ) is 1.8v to 5.5v higher than the negative power supply (v ss ). for normal operation, the other pins are between v ss and v dd . typically, these parts are used in a single (positive) supply configuration. in this case, v ss is connected to ground and v dd is connected to the supply; v dd will need bypass capacitors. 3.6 digital enable and v os calibration input this input (en/cal ) is a cmos, schmitt-triggered input that controls the active, low power and v os calibration modes of operation. when this pin goes low, the part is placed into a low power mode and the output is high-z. when this pin goes high, the amplifiers input offset voltage is corrected by the calibration circuitry, then the output is re-connected to the v out pin, which becomes low impedance, and the part resumes normal operation. 3.7 exposed thermal pad (ep) there is an internal connection between the exposed thermal pad (ep) and the v ss pin; they must be connected to the same potential on the printed circuit board (pcb). this pad can be connected to a pcb ground plane to provide a larger heat sink. this improves the package thermal resistance ( ja ). table 3-1: pin function table mcp6n11 symbol description soic tdfn 11 v fg feedback input 22 v im inverting input 33 v ip non-inverting input 44 v ss negative power supply 55 v ref reference input 66 v out output 77 v dd positive power supply 88 en/cal enable/v os calibrate digital input 9 ep exposed thermal pad (ep); must be connected to v ss downloaded from: http:///
mcp6n11 ds25073a-page 26 ? 2011 microchip technology inc. notes: downloaded from: http:///
? 2011 microchip technology inc. ds25073a-page 27 mcp6n11 4.0 applications the mcp6n11 instrumentation amplifier (ina) is manufactured using microchips state of the art cmos process. it is low cost, low power and high speed, making it ideal for battery-powered applications. 4.1 basic performance 4.1.1 standard circuit figure 4-1 shows the standard circuit configuration for these inas. when the inputs and output are in their specified ranges, the output voltage is approximately: equation 4-1: figure 4-1: standard circuit. for normal operation, keep: v ip , v im , v ref and v fg between v ivl and v ivh v ip C v im (i.e., v dm ) between v dml and v dmh v out between v ol and v oh 4.1.2 architecture figure 4-2 shows the block diagram for these inas. figure 4-2: mcp6n11 block diagram. the input offset voltage (v os ) is corrected by the voltage v tr . each time a v os calibration event occurs, v tr is updated to the best value (at that moment). these events are triggered by either powering up (monitored by the por) or by toggling the en/cal pin high. the current out of g m3 (i 3 ) is constant and very small (assumed to be zero in the following discussion). the input signal is applied to g m1 . equation 4-2 shows the relationships between the input voltages (v ip and v im ) and the common mode and differential voltages (v cm and v dm ). equation 4-2: the negative feedback loop includes g m2 , r m4 , r f and r g . these blocks set the dc open-loop gain (a ol ) and the nominal differential gain (g dm ): equation 4-3: a ol is very high, so i 4 is very small and i 1 + i 2 0. this makes the differential inputs to g m1 and g m2 equal in magnitude and opposite in polarity. ideally, this gives: equation 4-4: for an ideal part, changing v cm , v ss or v dd produces no change in v out . v ref shifts v out as needed. the different g min options change g m1 , g m2 and the internal compensation capacitor. this results in the performance trade-offs shown in tab l e 1 . v out v ref +g dm v dm where: g dm =1+r f /r g v out v ip v dd v im v ref v fg r f r g u 1 mcp6n11 r f v fg v out low power v ss v dd en/cal v out v os calibration v ref r m4 g m2 i 2 v ref i 4 g m3 i 3 v tr r g v ip v im g m1 i 1 v ip v im por v ip v cm v dm 2 ? + = v im v cm v dm 2 ? ? = v cm v ip v im + () 2 ? = v dm v ip v im ? = a ol g m2 r m4 = g dm 1r f r g ? + = v fg v ref ? () v dm = v out v dm g dm v ref + = downloaded from: http:///
mcp6n11 ds25073a-page 28 ? 2011 microchip technology inc. 4.1.3 dc errors section 1.5 explanation of dc error specs defines some of the dc error specifications. these errors are internal to the ina, and can be summarized as follows: equation 4-5: the non-linearity specs (inl cm and inl dm ) describe errors that are non-linear functions of v cm and v dm , respectively. they give the maximum excursion from linear response over the entire common mode and differential ranges. the input bias current and offset current specs (i b and i os ), together with a circuits external input resistances, give an additional dc error. figure 4-3 shows the resistors that set the dc bias point. figure 4-3: dc bias resistors. the resistors at the main input (r ip and r im ) and its input bias currents (i bp and i bm ) give the following changes in the inas bias voltages: equation 4-6: the best design results when r ip and r im are equal and small: equation 4-7: the resistors at the feedback input (r r , r f and r g ) and its input bias currents (i br and i bf ) give the following changes in the inas bias voltages: equation 4-8: the best design results when g dm r r and r f are equal and small: equation 4-9: where: v out v ref g dm 1g e + () v dm v ed + () + = g dm 1g e + () v e v e + () + where: psrr , cmrr and a ol are in units of v/v t a is in units of c v e v os v dd v ss ? psrr --------------------------------- v cm cmrr ---------------- - v ref cmrr ---------------- - ++ + = v out a ol ----------------- t a v os t a ------------- ? ++ v ed inl dm v dmh v dml ? () v e inl cm v ivh v ivl ? () v out v ip v dd v im v ref r f r g r ip r im r r i bp i bm v fg i bf i br u 1 mcp6n11 where: cmrr is in units of v/v v ip i bp r ip ? i b ? i os 2 ------- - ? ?? ?? r ip == v im i bm r im ? i b ? i os 2 ------- - + ?? ?? r im == v cm v ip v im + 2 -------------------------------- - = i ? b r ip r im + 2 ------------------------ - ?? ?? i ? os 2 ---------- - r ? ip r im + 2 ---------------------------- ?? ?? + = v dm v ip v im ? = i b r ? ip r im + () i os 2 ------- -r ip r im + () ? = v out g dm v dm v cm cmrr ---------------- - + ?? ?? = where: r ip = r im rtol = tolerance of r ip and r im v out g dm v dm g dm 2i b rtol i os ? () r ip where: i b2 meets the i b spec, but is not equal to i b i os2 meets the i os spec, but is not equal to i os v ref i br r r ? i b 2 ? i os 2 2 ---------- ? ?? ?? r r == v fg v ref , v out i b 2 r f g dm r r ? () i os 2 2 ---------- r f g dm r r + () + due to high a ol where: g dm r r = r f rtol = tolerance of r r , r f and r g v out 2 i b 2 rtol i os 2 + () () r f downloaded from: http:///
? 2011 microchip technology inc. ds25073a-page 29 mcp6n11 4.1.4 ac performance the bandwidth of these amplifiers depends on g dm and g min : equation 4-10: the bandwidth at the maximum output swing is called the full power bandwidth (f fpbw ). it is limited by the slew rate (sr) for many amplifiers, but is close to f bw for these parts: equation 4-11: cmrr is constant from dc to about 1 khz. 4.1.5 noise performance as shown in figures 2-41 and 2-42 , the 1/f noise causes an apparent wander in the dc output voltage. changing the measurement time or bandwidth has little effect on this noise. we recommend re-calibrating v os periodically, to reduce 1/f noise wander. for example, v os could be re-calibrated at least once every 15 minutes; more often when temperature or v dd change significantly. 4.2 functional blocks 4.2.1 rail-to-rail inputs each input stage uses one pmos differential pair at the input. the output of each differential pair is processed using current mode circuitry. the inputs show no crossover distortion vs. common mode voltage. with this topology, the inputs (v ip and v im ) operate normally down to v ss C 0.2v and up to v dd + 0.15v at room temperature (see figure 2-11 ). the input offset voltage (v os ) is measured at v cm =v ss C0.2v and v dd + 0.15v (at +25c), to ensure proper operation. 4.2.1.1 phase reversal the input devices are designed to not exhibit phase inversion when the input pins exceed the supply voltages. figures 2-18 and 2-50 show an input voltage exceeding both supplies with no phase inversion. the input devices also do not exhibit phase inversion when the differential input voltage exceeds its limits; see figures 2-22 and 2-51 . 4.2.1.2 input voltage limits in order to prevent damage and/or improper operation of these amplifiers, the circuit must limit the voltages at the input pins (see section 1.1 absolute maximum ratings ? ). this requirement is independent of the current limits discussed later on. the esd protection on the inputs can be depicted as shown in figure 4-4 . this structure was chosen to protect the input transistors against many (but not all) overvoltage conditions, and to minimize input bias current (i b ). figure 4-4: simplified analog input esd structures. where: f bw = -3 db bandwidth f gbwp = gain bandwidth product f bw f gbwp g dm --------------- 0.50 mhz () g min g dm ? () , 0.35 mhz () g min g dm ? () , g min =1, ,10 g min =100 where: v o = maximum output voltage swing v oh Cv ol f fpbw sr v o ---------- f bw , for these parts bond pad bond pad bond pad v dd v ip v ss input stage bond pad v im of ina input downloaded from: http:///
mcp6n11 ds25073a-page 30 ? 2011 microchip technology inc. the input esd diodes clamp the inputs when they try to go more than one diode drop below v ss . they also clamp any voltages that go too far above v dd ; their breakdown voltage is high enough to allow normal operation, but not low enough to protect against slow overvoltage (beyond v dd ) events. very fast esd events (that meet the spec) are limited so that damage does not occur. in some applications, it may be necessary to prevent excessive voltages from reaching the op amp inputs. figure 4-5 shows one approach to protecting these inputs. d 1 and d 2 may be small signal silicon diodes, schottky diodes for lower clamping voltages or diode- connected fets for low leakage. figure 4-5: protecting the analog inputs against high voltages. 4.2.1.3 input current limits in order to prevent damage and/or improper operation of these amplifiers, the circuit must limit the currents into the input pins (see section 1.1 absolute maxi- mum ratings ? ). this requirement is independent of the voltage limits previously discussed. figure 4-6 shows one approach to protecting these inputs. the resistors r 1 and r 2 limit the possible current in or out of the input pins (and into d 1 and d 2 ). the diode currents will dump onto v dd . figure 4-6: protecting the analog inputs against high currents. it is also possible to connect the diodes to the left of the resistor r 1 and r 2 . in this case, the currents through the diodes d 1 and d 2 need to be limited by some other mechanism. the resistors then serve as in-rush current limiters; the dc current into the input pins (v ip and v im ) should be very small. a significant amount of current can flow out of the inputs (through the esd diodes) when the common mode voltage (v cm ) is below ground (v ss ); see figure 2-25 . 4.2.1.4 input voltage ranges figure 4-7 shows possible input voltage values (v ss = 0v). lines with a slope of +1 have constant v dm (e.g., the v dm = 0 line). lines with a slope of -1 have constant v cm (e.g., the v cm =v dd /2 line). for normal operation, v ip and v im must be kept within the region surrounded by the thick blue lines. the horizontal and vertical blue lines show the limits on the individual inputs. the blue lines with a slope of +1 show the limits on v dm ; the larger g min is, the closer they are to the v dm = 0 line. the input voltage range specs (v ivl and v ivh ) change with the supply voltages (v ss and v dd , respectively). the differential input range specs (v dml and v dmh ) change with minimum gain (g min ). temperature also affects these specs. to take full advantage of v dml and v dmh , set v ref (see figure 1-6 and figure 1-7 ) so that the output (v out ) is centered between the supplies (v ss and v dd ). figure 4-7: input voltage ranges. v dd v 1 d 1 v 2 d 2 u 1 mcp6n11 min(r 1 ,r 2 )> v ss ?min(v 1 ,v 2 ) 2ma v dd v 1 r 1 d 1 v 2 r 2 d 2 u 1 mcp6n11 min(r 1 ,r 2 ) > max(v 1 ,v 2 )?v dd 2ma v ip v im v dm =0 v ivh v ivl 0 v ivh v ivl 0 v d m = v d m h v cm =v dd /2 v dm = v dmh v dd v dd downloaded from: http:///
? 2011 microchip technology inc. ds25073a-page 31 mcp6n11 4.2.2 enable/v os calibration (en/cal ) these parts have a normal mode, a low power mode and a v os calibration mode. when the en/cal pin is high and the internal por (with delay) indicates that power is good, the part operates in its normal mode. when the en/cal pin is low, the part operates in its low power mode. the quiescent current (at v ss ) drops to -2.5 a (typical), the amplifier output is put into a high-impedance state. signals at the input pins can feed through to the output pin. when the en/cal pin goes high and the internal por (with delay) indicates that power is good, the amplifier internally corrects its input offset voltage (v os ) with the internal common mode voltage at mid-supply (v dd /2) and the output tri-stated (after t off ). once v os calibra- tion is completed, the amplifier is enabled and normal operation resumes. the en/cal pin does not operate normally when left floating. either drive it with a logic output, or tie it high so that the part is always on. 4.2.3 por with delay the internal por makes sure that the input offset voltage (v os ) is calibrated whenever the supply voltage goes from low voltage (< v prl ) to high voltage (> v prh ). this prevents corruption of the v os trim reg- isters after a low-power event. after the por goes high, the internal circuitry adds a fixed delay (t plh ), before telling the v os calibration circuitry (see figure 4-2 ) to start. if the en/cal pin is toggled during this time, the fixed delay is restarted (takes an additional time t plh ). 4.2.4 parity detector a parity error detector monitors the memory contents for any corruption. in the rare event that a parity error is detected (e.g., corruption from an alpha particle), a por event is automatically triggered. this will cause the input offset voltage to be re-corrected, and the op amp will not return to normal operation for a period of time (the por turn on time, t plh ). 4.2.5 rail-to-rail output the minimum output voltage (v ol ) and maximum output voltage (v oh ) specs describe the widest output swing that can be achieved under the specified load conditions. the output can also be limited when v ip or v im exceeds v ivl or v ivh , or when v dm exceeds v dml or v dmh . 4.3 applications tips 4.3.1 minimum stable gain there are different options for different minimum stable gains (1, 2, 5, 10 and 100 v/v; see tab l e 1 - 1 ). the differential gain (g dm ) needs to be greater than or equal to g min in order to maintain stability. picking a part with higher g min has the advantages of lower input noise voltage density (e ni ), lower input offset voltage (v os ) and increased gain bandwidth product (gbwp); see table 1 . the differential input voltage range (v dmr ) is lower for higher g min , but the output voltage range would limit v dmr anyway, when g dm 2. 4.3.2 capacitive loads driving large capacitive loads can cause stability problems for amplifiers. as the load capacitance increases, the feedback loops phase margin decreases, and the closed-loop bandwidth is reduced. this produces gain peaking in the frequency response, with overshoot and ringing in the step response. lower gains (g dm ) exhibit greater sensitivity to capacitive loads. when driving large capacitive loads with these instrumentation amps (e.g., > 100 pf), a small series resistor at the output (r iso in figure 4-8 ) improves the feedback loops phase margin (stability) by making the output load resistive at higher frequencies. the bandwidth will be generally lower than the bandwidth with no capacitive load. figure 4-8: output resistor, r iso stabilizes large capacitive loads. figure 4-9 gives recommended r iso values for different capacitive loads and gains. the x-axis is the normalized load capacitance (c l g min /g dm ), where g dm is the circuits differential gain (1 + r f /r g ) and g min is the minimum stable gain. r iso v out c l v 1 v dd v 2 v ref v fg r f r g u 1 mcp6n11 downloaded from: http:///
mcp6n11 ds25073a-page 32 ? 2011 microchip technology inc. figure 4-9: recommended r iso values for capacitive loads. after selecting r iso for your circuit, double check the resulting frequency response peaking and step response overshoot on the bench. modify r iso s value until the response is reasonable. 4.3.3 gain resistors figure 4-10 shows a simple gain circuit with the inas input capacitances at the feedback inputs (v ref and v fg ). these capacitances interact with r g and r f to modify the gain at high frequencies. the equivalent capacitance acting in parallel to r g is c g =c dm +c cm plus any board capacitance in parallel to r g . c g will cause an increase in g dm at high frequencies, which reduces the phase margin of the feedback loop (i.e., reduce the feedback loop's stability). figure 4-10: simple gain circuit with parasitic capacitances. in this data sheet, r f +r g =10k for most gains (0 for g dm = 1); see table 1-6 . this choice gives good phase margin. in general, r f ( figure 4-10 ) needs to meet the following limits to maintain stability: equation 4-12: 4.3.4 supply bypass with these inas, the power supply pin (v dd for single supply) should have a local bypass capacitor (i.e., 0.01 f to 0.1 f) within 2 mm for good high frequency performance. surface mount, multilayer ceramic capacitors, or their equivalent, should be used. these inas require a bulk capacitor (i.e., 1.0 f or larger) within 100 mm, to provide large, slow currents. this bulk capacitor can be shared with other nearby analog parts as long as crosstalk through the supplies does not prove to be a problem. 1.e+03 1.e+04 o mmended r iso () 10k 1k 1.e+02 1.e-10 1.e-09 1.e-08 1.e-07 1.e-06 rec o normalized load capacitance; c l g min /g dm (f) 100 100p 1n 10n 100n 1 g min = 1 to 10 g min = 100 v out v 1 v dd v 2 v ref v fg r f r g c dm c cm c cm u 1 mcp6n11 where: 0.25 g dm g min f gbwp = gain bandwidth product c g = c dm + c cm + (pcb stray capacitance) r f 0= for g dm =1: r f g dm 2 2 f gbwp c g ------------------------------ < for g dm >1: downloaded from: http:///
? 2011 microchip technology inc. ds25073a-page 33 mcp6n11 4.4 typical applications 4.4.1 high input impedance difference amplifier figure 4-11 shows the mcp6n11 used as a difference amplifier. the inputs are high impedance and give good cmrr performance. figure 4-11: difference amplifier. 4.4.2 difference amplifier for very large common mode signals figure 4-12 shows the mcp6n11 ina used as a difference amplifier for signals with a very large common mode component. the input resistor dividers (r 1 and r 2 ) ensure that the voltages at the inas inputs are within their range of normal operation. the capacitors c 1 , with the parasitic capacitances c 2 (the resistors parasitic capacitance plus the inas input common mode capacitance, c cm ), set the same division ratio, so that high-frequency signals (e.g., a step in voltage) have the same gain. select the ina gain to compensate for r 1 and r 2 s attenuation. select r 1 and r 2 s tolerances for good cmrr. figure 4-12: difference amplifier with very large common mode component. 4.4.3 high side current detector figure 4-13 shows the mcp6n11 ina used as to detect and amplify the high side current in a battery powered design. the ina gain is set at 21 v/v, so v out changes 210 mv for every 1 ma of i dd current. the best g min option to pick would be a gain of 10 (mcp6n11-010). figure 4-13: high side current detector. 4.4.4 wheatstone bridge figure 4-14 shows the mcp6n11 single instrumentation amp used to condition the signal from a wheatstone bridge (e.g., strain gage). the overall ina gain is set at 201 v/v. the best g min option to pick, for this gain, is 100 v/v (mcp6n11-100). figure 4-14: wheatstone bridge amplifier. v out v ip v dd v im v ref v fg r f r g u 1 mcp6n11 v out v dd v ref v fg r f r g r 2 r 1 v 2 c 1 c 2 r 2 r 1 v 1 c 1 c 2 u 1 mcp6n11 i dd = (v bat ?v dd ) (10 ) = (v out ?v ref ) (10 ) (21.0 v/v) 10 v dd i dd v bat +1.8v to +5.5v v out v ref v fg r f r g 200 k 10 k u 1 mcp6n11 v out v ref v fg r f r g 200 k 1k v dd r w1 r w2 r w2 r w1 u 1 mcp6n11 downloaded from: http:///
mcp6n11 ds25073a-page 34 ? 2011 microchip technology inc. notes: downloaded from: http:///
? 2011 microchip technology inc. ds25073a-page 35 mcp6n11 5.0 design aids microchip provides the basic design aids needed for the mcp6n11 instrumentation amplifiers. 5.1 microchip advanced part selector (maps) maps is a software tool that helps efficiently identify microchip devices that fit a particular design requirement. available at no cost from the microchip website at www.microchip.com/maps , the maps is an overall selection tool for microchips product portfolio that includes analog, memory, mcus and dscs. using this tool, a customer can define a filter to sort features for a parametric search of devices and export side-by-side technical comparison reports. helpful links are also provided for data sheets, purchase and sampling of microchip parts. 5.2 analog demonstration board microchip offers a broad spectrum of analog demonstration and evaluation boards that are designed to help customers achieve faster time to market. for a complete listing of these boards and their corresponding users guides and technical information, visit the microchip web site at www.microchip.com/analog tools . 5.3 application notes the following microchip application notes are available on the microchip web site at www.microchip. com/appnotes and are recommended as supplemental reference resources. an884: ?driving capacitive loads with op amps? , ds00884 an990: ?analog sensor conditioning circuits ? an overview? , ds00990 an1228: ?op amp precision design: random noise? , ds01228 some of these application notes, and others, are listed in the design guide: ?signal chain design guide? , ds21825 downloaded from: http:///
mcp6n11 ds25073a-page 36 ? 2011 microchip technology inc. notes: downloaded from: http:///
? 2011 microchip technology inc. ds25073a-page 37 mcp6n11 6.0 packaging information 6.1 package marking information legend: xx...x customer-specific information y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week 01) nnn alphanumeric traceability code pb-free jedec designator for matte tin (sn) * this package is pb-free. the pb-free jedec designator ( ) can be found on the outer packaging for this package. note : in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 3 e 3 e 8-lead soic (150 mil) (mcp6n11) 8-lead tdfn (23) (mcp6n11) example device code mcp6n11-001 aaq mcp6n11-002 aar mcp6n11-005 aas mcp6n11-010 aat mcp6n11-100 aau note: applies to 8-lead 2x3 tdfn note: the example is for a mcp6n11-001 part. nnn 6n11001e sn^^ 1121 256 3 e aaq 121 25 example downloaded from: http:///
mcp6n11 ds25073a-page 38 ? 2011 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging downloaded from: http:///
? 2011 microchip technology inc. ds25073a-page 39 mcp6n11 note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging downloaded from: http:///
mcp6n11 ds25073a-page 40 ? 2011 microchip technology inc. downloaded from: http:///
? 2011 microchip technology inc. ds25073a-page 41 mcp6n11 note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging downloaded from: http:///
mcp6n11 ds25073a-page 42 ? 2011 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging downloaded from: http:///
? 2011 microchip technology inc. ds25073a-page 43 mcp6n11 downloaded from: http:///
mcp6n11 ds25073a-page 44 ? 2011 microchip technology inc. notes: downloaded from: http:///
? 2011 microchip technology inc. ds25073a-page 45 mcp6n11 appendix a: revision history revision a (october 2011) original release of this document. downloaded from: http:///
mcp6n11 ds25073a-page 46 ? 2011 microchip technology inc. notes: downloaded from: http:///
? 2011 microchip technology inc. ds25073a-page 47 mcp6n11 product identification system to order or obtain information, e. g., on pricing or delivery, refer to the factory or the listed sales office . device: mcp6n11 single instrumentation amplifier mcp6n11t single instrumentation amplifier (tape and reel) gain option: 001 = minimum gain of 1 v/v 002 = minimum gain of 2 v/v 005 = minimum gain of 5 v/v 010 = minimum gain of 10 v/v 100 = minimum gain of 100 v/v temperature range: e = -40c to +125c package: mny = 23 tdfn, 8-lead * sn = plastic soic (150mil body), 8-lead * y = nickel palladium gold manufacturing designator. only available on the tdfn package. examples: a) mcp6n11t-001e/mny: tape and reel, minimum gain = 1, extended temperature, 8ld 23 tdfn. b) mcp6n11-002e/sn: minimum gain = 2, extended temperature, 8ld soic. part no. Cx /xx package gain option device x temperature range downloaded from: http:///
mcp6n11 ds25073a-page 48 ? 2011 microchip technology inc. notes: downloaded from: http:///
? 2011 microchip technology inc. ds25073a-page 49 information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application meets with your specifications. microchip makes no representations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip devices in life support and/or safety applications is entirely at the buyers risk, and the buyer agrees to defend, indemnify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting from such use. no licenses are conveyed, implicitly or otherwise, under any microchip intellectual property rights. trademarks the microchip name and logo, the microchip logo, dspic, k ee l oq , k ee l oq logo, mplab, pic, picmicro, picstart, pic 32 logo, rfpic and uni/o are registered trademarks of microchip technology incorporated in the u.s.a. and other countries. filterlab, hampshire, hi-tech c, linear active thermistor, mxdev, mxlab, seeval and the embedded control solutions company are registered trademarks of microchip technology incorporated in the u.s.a. analog-for-the-digital age, application maestro, chipkit, chipkit logo, codeguard, dspicdem, dspicdem.net, dspicworks, dsspeak, ecan, economonitor, fansense, hi-tide, in-circuit serial programming, icsp, mindi, miwi, mpasm, mplab certified logo, mplib, mplink, mtouch, omniscient code generation, picc, picc-18, picdem, picdem.net, pickit, pictail, real ice, rflab, select mode, total endurance, tsharc, uniwindriver, wiperlock and zena are trademarks of microchip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of microchip technology incorporated in the u.s.a. all other trademarks mentioned herein are property of their respective companies. ? 2011, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. isbn: 978-1-61341-685-3 note the following details of the code protection feature on microchip devices: microchip products meet the specification cont ained in their particular microchip data sheet. microchip believes that its family of products is one of the most secure families of its kind on the market today, when used i n the intended manner and under normal conditions. there are dishonest and possibly illegal methods used to breach the code protection feature. all of these methods, to our knowledge, require using the microchip products in a manner outside the operating specif ications contained in microchips data sheets. most likely, the person doing so is engaged in theft of intellectual property. microchip is willing to work with the customer who is concerned about the integrity of their code. neither microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as unbreakable. code protection is constantly evolving. we at microchip are co mmitted to continuously improvin g the code protection features of our products. attempts to break microchips code protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona; gresham, oregon and design centers in california and india. the company?s quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microperipherals, nonvolatile memory an d analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified. downloaded from: http:///
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